SPIFLASH
========

Register Listing for SPIFLASH
-----------------------------

+--------------------------------------------------+-----------------------------------------+
| Register                                         | Address                                 |
+==================================================+=========================================+
| :ref:`SPIFLASH_BITBANG <SPIFLASH_BITBANG>`       | :ref:`0xe0002800 <SPIFLASH_BITBANG>`    |
+--------------------------------------------------+-----------------------------------------+
| :ref:`SPIFLASH_MISO <SPIFLASH_MISO>`             | :ref:`0xe0002804 <SPIFLASH_MISO>`       |
+--------------------------------------------------+-----------------------------------------+
| :ref:`SPIFLASH_BITBANG_EN <SPIFLASH_BITBANG_EN>` | :ref:`0xe0002808 <SPIFLASH_BITBANG_EN>` |
+--------------------------------------------------+-----------------------------------------+

SPIFLASH_BITBANG
^^^^^^^^^^^^^^^^

`Address: 0xe0002800 + 0x0 = 0xe0002800`

    Bitbang controls for SPI output.  Only standard 1x SPI is supported, and as a
    result all four wires are ganged together.  This means that it is only possible
    to perform half-duplex operations, using this SPI core.

    .. wavedrom::
        :caption: SPIFLASH_BITBANG

        {
            "reg": [
                {"name": "mosi",  "bits": 1},
                {"name": "clk",  "bits": 1},
                {"name": "cs_n",  "bits": 1},
                {"name": "dir",  "bits": 1},
                {"bits": 28}
            ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4}
        }


+-------+------+----------------------------------------------------------------+
| Field | Name | Description                                                    |
+=======+======+================================================================+
| [0]   | MOSI | Output value for MOSI pin, valid whenever ``dir`` is ``0``.    |
+-------+------+----------------------------------------------------------------+
| [1]   | CLK  | Output value for SPI CLK pin.                                  |
+-------+------+----------------------------------------------------------------+
| [2]   | CS_N | Output value for SPI CSn pin.                                  |
+-------+------+----------------------------------------------------------------+
| [3]   | DIR  | Sets the direction for *ALL* SPI data pins except CLK and CSn. |
|       |      |                                                                |
|       |      | +-------+-------------------------+                            |
|       |      | | Value | Description             |                            |
|       |      | +=======+=========================+                            |
|       |      | | 0     | SPI pins are all output |                            |
|       |      | +-------+-------------------------+                            |
|       |      | | 1     | SPI pins are all input  |                            |
|       |      | +-------+-------------------------+                            |
+-------+------+----------------------------------------------------------------+

SPIFLASH_MISO
^^^^^^^^^^^^^

`Address: 0xe0002800 + 0x4 = 0xe0002804`

    Incoming value of MISO signal.

    .. wavedrom::
        :caption: SPIFLASH_MISO

        {
            "reg": [
                {"name": "miso", "bits": 1},
                {"bits": 31},
            ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4}
        }


SPIFLASH_BITBANG_EN
^^^^^^^^^^^^^^^^^^^

`Address: 0xe0002800 + 0x8 = 0xe0002808`

    Write a ``1`` here to disable memory-mapped mode and enable bitbang mode.

    .. wavedrom::
        :caption: SPIFLASH_BITBANG_EN

        {
            "reg": [
                {"name": "bitbang_en", "bits": 1},
                {"bits": 31},
            ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4}
        }