SPIFLASH

Register Listing for SPIFLASH

Register	Address
SPIFLASH_BITBANG	0xe0002800
SPIFLASH_MISO	0xe0002804
SPIFLASH_BITBANG_EN	0xe0002808

SPIFLASH_BITBANG

Address: 0xe0002800 + 0x0 = 0xe0002800

Bitbang controls for SPI output. Only standard 1x SPI is supported, and as a result all four wires are ganged together. This means that it is only possible to perform half-duplex operations, using this SPI core.

Field	Name	Description
[0]	MOSI	Output value for MOSI pin, valid whenever dir is 0.
[1]	CLK	Output value for SPI CLK pin.
[2]	CS_N	Output value for SPI CSn pin.
[3]	DIR	Sets the direction for ALL SPI data pins except CLK and CSn. Value Description 0 SPI pins are all output 1 SPI pins are all input

SPIFLASH_MISO

Address: 0xe0002800 + 0x4 = 0xe0002804

Incoming value of MISO signal.

SPIFLASH_BITBANG_EN

Address: 0xe0002800 + 0x8 = 0xe0002808

Write a 1 here to disable memory-mapped mode and enable bitbang mode.